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etrontech em63 b 165 ts etron technology, inc. no. 6, technology rd. v, hsinchu science park, hsinchu, taiwan 3007 8 , r.o.c. tel: (886) - 3 - 5782345 fax: (886) - 3 - 5778671 etron t echnology, inc. reserves the right to change products or specification without notice. 32 m x 16 bit synchronous dram (sdram) advance ( rev . 2 .0 , jun . / 20 1 6 ) features ? fast access time from clock: 4.5/ 5/ 5.4 ns ? ? ? ? ? ? ? ? ? 0.3v power supply ? a = - 4 0~ 85 c ? ? table 1. key specifications table 2. ordering information overview the em63 b 165 sdram is a high - speed cmos synchronous dram containing 512 mbits. it is internally configured as 4 banks of 8 m w ord x 16 dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of lo cations in a programmed sequence. accesses begin with the registration of a bank activate command which is then followed by a read or write command. the em63 b 165 provides for programmable read or write burst lengths of 1, 2, 4, 8, or full page, with a burs t termination option. an auto precharge function may be enabled to provide a self - timed row precharge that is initiated at the end of the burst sequence. the refresh functions, either auto or self refresh are easy to use. by having a programmable mode regi ster, the system can choose the most suitable modes to maximize its performance. these devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance pc applications. em63 b 165 - 5 i / 6 i /7 i tck3 clock cycle time(min.) 5/ 6 /7 ns tac3 access time from clk (max.) 4. 5 /5/5.4 n s tras row active time( min .) 40/ 42 /4 2 ns trc row cycle time(min.) 55/ 60/ 63 ns part number frequency package em63 b 165ts - 5 i s g 200 mhz tsop ii em63 b 165ts - 6 is g 166mhz tsop ii em63 b 165ts - 7 is g 1 4 3mhz tsop ii ts: indicates tsopii package i : in dicates industrial grade s: indicates stacked dice g: indicates pb and halogen free
etrontech em63 b 165 ts rev . 2.0 2 jun . / 20 16 figure 1. pin assignment (t op view) 1 54 vdd vss 2 53 dq 0 dq 15 3 52 vddq vssq 4 51 dq 1 dq 14 5 50 dq 2 dq 13 6 49 vssq vddq 7 48 dq 3 dq 12 8 47 dq 4 dq 11 9 46 vddq vssq 10 45 dq 5 dq 10 11 44 dq 6 dq 9 12 43 vssq vddq 13 42 dq 7 dq 8 14 41 vdd vss 15 40 ldqm nc 16 39 we # udqm 17 38 cas # clk 18 37 ras # cke 19 36 cs # a 12 20 35 ba 0 a 11 21 34 ba 1 a 9 22 33 a 10 / ap a 8 23 32 a 0 a 7 24 31 a 1 a 6 25 30 a 2 a 5 26 29 a 3 a 4 27 28 vdd vss
etrontech em63 b 165 ts rev . 2.0 3 jun . / 20 16 figure 2 . block diagram c l k c k e c s # r a s # c a s # w e # c l o c k b u f f e r c o m m a n d d e c o d e r c o l u m n c o u n t e r c o n t r o l s i g n a l g e n e r a t o r a d d r e s s b u f f e r r e f r e s h c o u n t e r b u f f e r 8 m x 1 6 c e l l a r r a y ( b a n k # a ) r o w d e c o d e r 8 m x 1 6 c e l l a r r a y ( b a n k # b ) r o w d e c o d e r 8 m x 1 6 c e l l a r r a y ( b a n k # c ) r o w d e c o d e r 8 m x 1 6 c e l l a r r a y ( b a n k # d ) r o w d e c o d e r c o l u m n d e c o d e r c o l u m n d e c o d e r c o l u m n d e c o d e r c o l u m n d e c o d e r m o d e r e g i s t e r d q 1 5 d q 0 ~ a 1 0 / a p a 9 a 1 1 a 1 2 b a 0 b a 1 ~ a 0 l d q m , u d q m
etrontech em63 b 165 ts rev . 2.0 4 jun . / 20 16 pin descriptions table 3 . pin details symbol type description clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. cke input clock enable: cke activates (high) and deactivates (low) the clk signal. if cke goes low synchronously with clock (set - up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating the clock controls the entry to the power down and sel f refresh modes. cke is synchronous except after the device enters power down and self refresh modes, where cke becomes asynchronous until exiting the same mode. the input buffers, including clk, are disabled during power down and self refresh modes, provi ding low standby power. ba0,ba1 input bank activate : ba0, ba1 input select the bank for operation. ba1 ba0 select bank 0 0 bank #a 0 1 bank #b 1 0 bank #c 1 1 bank #d a0 - a1 2 input address inputs: a0 - a1 2 are sampled during the bankactivate command (row address a0 - a1 2 ) and read/write command (column address a0 - a 9 with a10 defining auto precharge) to select one location out of the 8 m available in the respective bank. during a precharge command, a10 is sampled to determine if all banks are to be precharged (a10 = high). the address inputs also provide the op - code during a mode register set command. cs# input chip select: cs# enables (sampled low) and disables (sampled high) the command decoder. all commands are masked when cs# is sampled high. cs# provides for external bank selection on systems with multiple banks. it is considered part of the command code. ras# input row address strobe: the ras# signal defines the operation commands in conjunction with the cas# and we# signals and is latched at the positive edges of clk. when ras# and cs# are asserted " low" and cas# is asserted "high " either the bankactivate command or the precharge command is selected by the we# signal. when the we# is asserted "high " the bankactivate command is selected and the bank designated by b a is turned on to the active state . when the we# is asserted "low " the precharge command is selected and the bank designated by b a is switched to the idle state after the precharge operation. cas# input column address strobe: the c as# signal defines the operation commands in conjunction with the ras# and we# signals and is latched at the positive edges of clk. when ras# is held "high" and cs# is asserted "low " the column access is started by asserting cas# "low " . then, the read or w rite command is selected by asserting we# "low " or "high " . we# input write enable: the we# signal defines the operation commands in conjunction with the ras# and cas# signals and is latched at the positive edges of clk. the we# input is used to select the bankactivate or precharge command and read or write command. ldqm, udqm input data input/output mask: controls output buffers in read mode and masks input data in write mode.
etrontech em63 b 165 ts rev . 2.0 5 jun . / 20 16 dq0 - dq15 input / output data i/o: the dq0 - 15 input and output data are synchr onized with the positive edges of clk. the i/os are maskable d during reads and writes. nc - no connect: these pins should be left unconnected. v ddq suply dq power: provide isolated power to d qs for improved noise immunity. ( + 3.3v ? 0.3v ) v ssq supply dq g round: provide isolated ground to dqs for improved noise immunity. (0 v ) v dd supply power supply: + 3.3v ? 0.3v v ss supply ground
etrontech em63 b 165 ts rev . 2.0 6 jun . / 20 16 operation mode fully synchronous operations are performed to latch the commands at the positive edges of clk . table 4 shows the truth table for the operation commands. tabl e 4 . truth table (note (1), (2) ) command state cke n - 1 cke n dqm ba 0,1 a 10 a 0 - 9, 11 - 1 2 cs# ras# cas# we# bankactivate idle (3) h x x v row address l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write active (3) h x v v l column address (a0 ~ a 9 ) l h l l write and autoprecharge active (3) h x v v h l h l l read active (3) h x v v l column address (a0 ~ a 9 ) l h l h read and autoprecharg e active (3) h x v v h l h l h mode register set idle h x x op code l l l l no - operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x autorefresh idle h h x x x x l l l h selfrefresh entry i dle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x (selfrefresh) l h h h clock suspend mode entry active h l x x x x h x x x l v v v power down mode entry any (5) h l x x x x h x x x l h h h clock suspend mode ex it active l h x x x x x x x x power down mode exit any l h x x x x h x x x (powerdown) l h h h data write/output enable active h x l x x x x x x x data mask/output disable active h x h x x x x x x x note: 1. v= valid , x =don't care , l =low level , h=high level 2. cke n signal is input level when commands are provided. cke n - 1 signal is input level one clock cycle before the commands are provided. 3. these are states of bank designated by b a signal. 4. device state is 1, 2, 4, 8, and full page burst op eration. 5. power down mode can not enter in the burst operation. when this command is asserted in the burst cycle, device state is clock suspend mode.
etrontech em63 b 165 ts rev . 2.0 7 jun . / 20 16 commands 1 bankactivate (ras# = "l", cas# = "h", we# = "h", bas = bank, a0 - a1 2 = row address) t he bankactivate command activates the idle bank designated by the ba0 , 1 signals . by latching the row address on a0 to a1 2 at the time of this command, the selected row access is initiated. the read or write operation in the same bank can occur after a tim e delay of t rcd (min.) from the time of bank activation. a subsequent bankactivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). the minimum time interval be tween successive bankactivate commands to the same bank is defined by t rc (min.). the sdram has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back - to - back activation of the two banks. t rrd (min.) specifies the minimum time required between activating different banks. after this command is used, the write command and the block write command perform the no mask write operation. figure 3 . bankactiva te command cycle (burst length = n) 2 bankprecharge command (ras# = "l", cas# = "h", we# = "l", bas = bank, a10 = "l", a0 - a9 , a11 and a12 = don't care) the bankprecharge command precharges the bank disignated by ba signal. the precharged bank is swit ched from the active state to the idle state. this command can be asserted anytime after t ras (min.) is satisfied from the bankactivate command in the desired bank. the maximum time any bank can be active is specified by t ras (max.). therefore, the precharge function must be performed in any active bank within t ras (max.). at the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. 3 prechargeall command (ras# = "l", cas# = "h", we# = "l", bas = dont care, a1 0 = "h", a0 - a9 , a11 and a12 = don't care) the prechargeall command precharges all banks simultaneously and can be issued even if all banks are not in the active state. all banks are then switched to the idle state. 4 read command (ras# = "h", cas# = "l", we# = "h", bas = bank, a10 = "l", a0 - a 9 = column address) the read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the read command is issued. during read bursts, the valid data - out element from the starting column address will be available following the cas latency after the issue of the read command. each subsequent data - out element will be valid by the next positive clock edge (refer t o the following figure). the dqs go into high - impedance at the end of the burst unless other command is initiated. the burst length, burst sequence, and cas latency are determined by the mode register, which is already programmed. a full - page burst will co ntinue until terminated (at the end of the page it will wrap to column 0 and continue). c l k c o m m a n d t 0 t 1 a d d r e s s t 2 t 3 t n + 3 t n + 4 t n + 5 t n + 6 r a s # - c a s # d e l a y ( t r c d ) r a s # - r a s # d e l a y t i m e ( t r r d ) r a s # - c y c l e t i m e ( t r c ) a u t o p r e c h a r g e b e g i n b a n k a r o w a d d r . b a n k a c o l a d d r . b a n k b r o w a d d r . b a n k a r o w a d d r . b a n k a a c t i v a t e n o p n o p r / w a w i t h a u t o p r e c h a r g e b a n k b a c t i v a t e n o p n o p b a n k a a c t i v a t e d o n t c a r e
etrontech em63 b 165 ts rev . 2.0 8 jun . / 20 16 figure 4 . burst read operation ( burst length = 4, cas# latency = 2, 3) the read data appears on the dqs subject to the values on t he dqm inputs two clocks earlier (i.e. dqm latency is two clocks for output buffers). a read burst without the auto precharge function may be interrupted by a subsequent read or write command to the same bank or the other active bank before the end of the burst length. it may be interrupted by a bankprecharge/ prechargeall command to the same bank too. the interrupt coming from the read command can occur on any clock cycle following a previous read command (refer to the following figure). figure 5 . read interrupted by a read (burst length = 4, cas# latency = 2, 3) the dqm inputs are used to avoid i/o contention on the dq pins when the interrupt comes from a write command. the dqms must be asserted (high) at least two clo cks prior to the write command to suppress data - out on the dq pins. to guarantee the dq pins against i/o contention, a single cycle with high - impedance on the dq pins must occur between the last read data and the write command (refer to the following three figures). if the data output of the burst read occurs at the second clock of the burst write, the dqms must be asserted (high) at least one clock prior to the write command to avoid internal bus contention. figure 6 . read to write interval (burst length ? c l k c o m m a n d t 0 t 1 t 2 t 3 t 4 t 5 t 6 r e a d a n o p n o p n o p n o p n o p n o p n o p t 7 t 8 n o p c a s # l a t e n c y = 2 t c k 2 , d q c a s # l a t e n c y = 3 t c k 3 , d q d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 c l k c o m m a n d t 0 t 1 t 2 t 3 t 4 t 5 t 6 r e a d a r e a d b n o p n o p n o p n o p n o p n o p t 7 t 8 n o p c a s # l a t e n c y = 2 t c k 2 , d q c a s # l a t e n c y = 3 t c k 3 , d q d o u t a 0 d o u t b 0 d o u t b 1 d o u t b 2 d o u t a 0 d o u t b 0 d o u t b 1 d o u t b 2 d o u t b 3 d o u t b 3 c l k c o m m a n d t 0 t 1 t 2 t 3 t 4 t 5 t 6 n o p n o p b a n k a a c t i v a t e n o p n o p r e a d a w r i t e a n o p t 7 t 8 n o p c a s # l a t e n c y = 2 t c k 2 , d q d q m t 9 n o p d i n a 0 d i n a 1 d i n a 2 d i n a 3
etrontech em63 b 165 ts rev . 2.0 9 jun . / 20 16 figure 7 . read to write interval (burst length ? figur e 8 . r ead to write interval (burst length R a read burst without the auto precharge function may be interrupted by a bankprecharge/ prechargeall command to the same bank. the following figure shows the optimum time that bank precharge/ prechargeall command is issued in dif ferent cas latency. figure 9 . read to precharge (cas# latency = 2, 3) c l k c o m m a n d t 0 t 1 t 2 t 3 t 4 t 5 t 6 n o p n o p r e a d a n o p n o p w r i t e b n o p n o p t 7 t 8 n o p d q m d i n b 0 d i n b 1 d i n b 2 d i n b 3 c a s # l a t e n c y = 2 t c k 2 , d q m u s t b e h i - z b e f o r e t h e w r i t e c o m m a n d d o n t c a r e c l k c o m m a n d t 0 t 1 t 2 t 3 t 4 t 5 t 6 n o p r e a d a n o p n o p n o p n o p w r i t e b n o p t 7 t 8 n o p d q m d o u t a 0 d i n b 0 d i n b 1 d i n b 2 c a s # l a t e n c y = 3 t c k 3 , d q m u s t b e h i - z b e f o r e t h e w r i t e c o m m a n d d o n t c a r e c l k c o m m a n d t 0 t 1 t 2 t 3 t 4 t 5 t 6 r e a d a n o p n o p n o p p r e c h a r g e n o p n o p a c t i v a t e t 7 t 8 n o p c a s # l a t e n c y = 2 t c k 2 , d q c a s # l a t e n c y = 3 t c k 3 , d q d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 a d d r e s s b a n k , c o l a b a n k ( s ) b a n k r o w t r p
etrontech em63 b 165 ts rev . 2.0 10 jun . / 20 16 5 read and autoprecharge command (ras# = "h", cas# = "l", we# = "h", bas = bank, a10 = "h", a0 - a 9 = column address) the read and autoprecharge command automatically performs the precharge operation after the read operation. once this command is given, any subsequent command cannot occur within a time delay of { t rp (min.) + burst length } . at full - page burst, only the read operation is performed in this command and the auto precharge function is ignored. 6 write command (ras# = "h", cas# = "l", we# = "l", bas = bank, a10 = "l", a0 - a 9 = column address) the write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the write command is issued. during write bursts, the first valid data - in element will be registered coincident with the write command. subsequent data elements will be register ed on each successive positive clock edge (refer to the following figure). the dqs remain with high - impedance at the end of the burst unless another command is initiated. the burst length and burst sequence are determined by the mode register, which is alr eady programmed. a full - page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). figure 1 0 . burst write operation (burst length = 4) a write burst without the auto prec harge function may be interrupted by a subsequent write, bankprecharge/prechargeall, or read command before the end of the burst length. an interrupt coming from write command can occur on any clock cycle following the previous write command (refer to the following figure). figure 1 1 . write interrupted by a write (burst length = 4) the read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which t he last data - in element is registered. in order to avoid data contention, input data must be removed from the dqs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). once the read command is registere d, the data inputs will be ignored and writes will not be executed. c l k d q t 0 t 1 t 2 t 3 t 4 t 5 t 6 d i n a 0 d i n a 1 d i n a 2 d i n a 3 d o n t c a r e t 7 t 8 c o m m a n d n o p w r i t e a n o p n o p n o p n o p n o p n o p n o p t h e f i r s t d a t a e l e m e n t a n d t h e w r i t e a r e r e g i s t e r e d o n t h e s a m e c l o c k e d g e c l k d q t 0 t 1 t 2 t 3 t 4 t 5 t 6 d i n a 0 d i n b 0 d i n b 1 d i n b 2 d i n b 3 t 7 t 8 c o m m a n d n o p w r i t e a w r i t e b n o p n o p n o p n o p n o p n o p
etrontech em63 b 165 ts rev . 2.0 11 jun . / 20 16 figure 1 2 . write interrupted by a read (burst length = 4, cas# latency = 2, 3) the bankprecharge/prechargeall command that interrupts a write burst with out the auto precharge function should be issued m cycles after the clock edge in which the last data - in element is registered, where m equals t wr /t ck rounded up to the next whole number. in addition, the dqm signals must be used to mask input data, starti ng with the clock edge following the last data - in element and ending with the clock edge on which the bankprecharge/prechargeall command is entered (refer to the following figure). note: the dqms can remain low in this examp le if the length of the write burst is 1 or 2. figure 1 3 . write to precharge 7 write and autoprecharge command (ras# = "h", cas# = "l", we# = "l", bas = bank, a10 = "h", a0 - a 9 = column address) the write and autoprecharge command perform s the precharge operation automatically after the write operation. once this command is given, any subsequent command can not occur within a time delay of { (burst length - 1) + t wr + t rp (min.) } . at full - page burst, only the write operation is performed in t his command and the auto precharge function is ignored. c l k c o m m a n d t 0 t 1 t 2 t 3 t 4 t 5 t 6 n o p w r i t e a r e a d b n o p n o p n o p n o p n o p t 7 t 8 n o p c a s # l a t e n c y = 2 t c k 2 , d q c a s # l a t e n c y = 3 t c k 3 , d q d o u t b 0 d o u t b 1 d o u t b 2 d o u t b 3 d o u t b 0 d o u t b 1 d o u t b 2 d o u t b 3 d i n a 0 d o n t c a r e d i n a 0 d o n t c a r e d o n t c a r e i n p u t d a t a m u s t b e r e m o v e d f r o m t h e d q a t l e a s t o n e c l o c k c y c l e b e f o r e t h e r e a d d a t a a p p e a r s o n t h e o u t p u t s t o a v o i d d a t a c o n t e n t i o n c l k c o m m a n d t 0 t 1 t 2 t 3 t 4 t 5 t 6 w r i t e n o p n o p p r e c h a r g e n o p n o p a c t i v a t e n o p t 7 d q m d o n t c a r e a d d r e s s b a n k c o l n b a n k ( s ) r o w t r p d i n n d i n n + 1 t w r d q
etrontech em63 b 165 ts rev . 2.0 12 jun . / 20 16 figure 1 4 . burst write with auto - precharge (burst length = 2) 8 mode register set command (ras# = "l", cas# = "l", we# = "l", a0 - a1 2 = register data) the mode reg ister stores the data for controlling the various operating modes of sdram. the mode register set command programs the values of cas latency, addressing mode and burst length in the mode register to make sdram useful for a variety of different applications . the default values of the mode register after power - up are undefined; therefore this command must be issued at the power - up sequence. the state of pins a0~ a1 2 in the same cycle is the data written to the mode register. two clock cycle s are required to c omplete the write in the mode register (refer to the following figure). the contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state. table 5 . mode regi ster bitmap ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 rfu* 0 rfu* wbl test mode cas latency bt burst lengt h a9 write burst length a8 a7 test mode a3 burst type 0 burst 0 0 normal 0 sequential 1 single bit 1 0 vendor use only 1 interleave 0 1 vendor use only a6 a5 a4 cas latency a2 a1 a0 burst length 0 0 0 reserved 0 0 0 1 0 0 1 reserved 0 0 1 2 0 1 0 2 clocks 0 1 0 4 0 1 1 3 clocks 0 1 1 8 1 0 0 reserved 1 1 1 full page (sequential ) all o ther reserved all other reserved *note: rfu (reserved for future use) should stay 0 during mrs cycle. c l k d q t 0 t 1 t 2 t 3 t 4 t 5 t 6 d i n a 0 d i n a 1 t 7 t 8 c o m m a n d b a n k a a c t i v a t e n o p n o p w r i t e a a u t o p r e c h a r g e n o p n o p n o p n o p n o p t 9 b a n k a a c t i v a t e t d a l = t w r + t r p t d a l b e g i n a u t o p r e c h a r g e b a n k c a n b e r e a c t i v a t e d a t c o m p l e t i o n o f t d a l
etrontech em63 b 165 ts rev . 2.0 13 jun . / 20 16 figure 1 5 . mode register set cycle ? burst length field (a2~a0) this field specifies the data length of column access using the a2~a0 pins and selects the burst length to be 2, 4, 8, or full page. table 6. burst length field a2 a1 a0 burst length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 res erved 1 1 1 full page full page length: 512 c l k c s # t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c k e d o n t c a r e r a s # t m r d c a s # t 8 t 9 t 1 0 w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q t r p p r e c h a r g e a l l m o d e r e g i s t e r s e t c o m m a n d a n y c o m m a n d h i - z a d d r e s s k e y
etrontech em63 b 165 ts rev . 2.0 14 jun . / 20 16 ? burst type field (a3) the addressing mode can be one of two modes, interleave mode or sequential mode. sequential mode supports burst length of 1, 2, 4, 8, or full page, but interleave mode only supports burst length of 4 and 8. table 7. addressing mode select field a3 burst type 0 sequential 1 interleave ? burst definition, addressing sequence of sequential and interleave mode table 8. bur st definition burst length start address sequential interleave a2 a1 a0 2 x x 0 0, 1 0, 1 x x 1 1, 0 1, 0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4 , 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 full page location = 0 - 511 n, n+1, n+2, n+3, ? cas latency field (a6~a4) this field specifies the number of clock cycles from the assertion of the read command to the first read data. the minimum whole value of cas latency depends on the frequency of clk. the minimum whole value satisfying the following formula must be programmed into this field. t cac (min) ? cas latency x t ck table 9. cas latency a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 x x reserved
etrontech em63 b 165 ts rev . 2.0 15 jun . / 20 16 ? test mode field (a8~a7) these two bits are used to enter the test mode and must be programmed to "00" in normal operation. table 10. test mode a8 a7 test mode 0 0 normal mode 0 1 vendor use only 1 x vendor use only ? write burst length (a9) this bit is used to select the write burst l ength . when the a9 bit is "0", the burst - read - burst - write mode is selected. when the a9 bit is "1", the burst - read - single - write mode is selected. table 11. write burst length a9 write b urst length 0 burst - read - burst - write 1 burst - read - single - write note: a10 and ba0 , 1 should stay l during mode set cycle. 9 no - operation command (ras# = "h", cas# = "h", we# = "h") the no - operation command is used to perform a nop to the sdram whi ch is selected (cs# is low). this prevents unwanted commands from being registered during idle or wait states. 10 burst stop command (ras# = "h", cas# = "h", we# = "l") the burst stop command is used to terminate either fixed - length or full - page bur sts. this command is only effective in a read/write burst without the auto precharge function. the terminated read burst ends after a delay equal to the cas latency (refer to the following figure). the termination of a write burst is shown in the following figure. figure 1 6 . termination of a burst read operation (burst length c l k c o m m a n d t 0 t 1 t 2 t 3 t 4 t 5 t 6 r e a d a n o p n o p n o p b u r s t s t o p n o p n o p n o p t 7 t 8 n o p c a s # l a t e n c y = 2 t c k 2 , d q c a s # l a t e n c y = 3 t c k 3 , d q d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 t h e b u r s t e n d s a f t e r a d e l a y e q u a l t o t h e c a s # l a t e n c y
etrontech em63 b 165 ts rev . 2.0 16 jun . / 20 16 figure 1 7 . termination of a burst write operation (burst length = x ) 11 device deselect command (cs# = "h") the device deselect command disables the command decoder so that the ras#, cas#, we# and address inputs are ignored, regardless of whether the clk is enabled. this command is similar to the no operation command. 12 autorefresh command (ras# = "l", cas# = "l", we# = "h" , cke = "h", a0 - a 12 = don't care) the autorefresh command is used during normal operation of the sdram and is analogous to cas# - before - ras# (cbr) refresh in conventional drams. this command i s non - persistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a "don't care" during an autorefresh command. the internal refresh counter increments automa tically on every auto refresh cycle to all of the rows. the refresh operation must be performed 819 2 times within 64 ms. the time required to complete the auto refresh operation is specified by t rc (min.). to provide the autorefresh command, all banks need t o be in the idle state and the device must not be in power down mode (cke is high in the previous cycle). this command must be followed by nops until the auto refresh operation is completed. the precharge time requirement, t rp (min), must be met before succ essive auto refresh operations are performed. 13 selfrefresh entry command (ras# = "l", cas# = "l", we# = "h", cke = "l", a0 - a 12 = don't care) the selfrefresh is another refresh mode available in the sdram. it is the preferred refresh mode for data retention and low power operation. once the selfrefresh command is registered, all the inputs to the sdram become "don't care" with the exception of cke, which must remain low. the refresh addressing and timing is internally generated to reduce power consu mption. the sdram may remain in selfrefresh mode for an indefinite period. the selfrefresh mode is exited by restarting the external clock and then asserting high on cke (selfrefresh exit command). 14 selfrefresh exit command this command is used to ex it from the selfrefresh mode. once this command is registered, nop or device deselect commands must be issued for t xsr (min.) because time is required for the completion of any bank currently being internally refreshed. if auto refresh cycles in bursts are performed during normal operation, a burst of 819 2 auto refresh cycles should be completed just prior to entering and just after exiting the selfrefresh mode. 15 clock suspend mode entry / powerdown mode entry command (cke = "l") when the sdram is oper ating the burst cycle, the internal clk is suspended (masked) from the subsequent cycle by issuing this command (asserting cke "low"). the device operation is held intact while clk is suspended. on the other hand, when all banks are in the idle state, this command performs entry into the powerdown mode. all input and output buffers (except the cke buffer) are turned off in the powerdown mode. the device may not remain in the clock suspend or powerdown state longer than the refresh period (64ms) since the co mmand does not perform any refresh operations. c l k d q t 0 t 1 t 2 t 3 t 4 t 5 t 6 d i n a 0 d i n a 1 d i n a 2 d o n t c a r e t 7 t 8 c o m m a n d n o p w r i t e a n o p n o p b u r s t s t o p n o p n o p n o p n o p
etrontech em63 b 165 ts rev . 2.0 17 jun . / 20 16 16 clock suspend mode exit / powerdown mode exit command (cke= "h") when the internal clk has been suspended, the operation of the internal clk is reinitiated from the subsequent cycle by providing this command (asserting cke "high" , the command should be nop or deselect ). when the device is in the powerdown mode, the device exits this mode and all disabled buffers are turned on to the active state. t pde (min.) is required when the device exits from the p owerdown mode. any subsequent commands can be issued after one clock cycle from the end of this command. 17 data write / output enable, data mask / output disable command (dqm = "l", "h") during a write cycle, the dqm signal functions as a data mask an d can control every word of the input data. during a read cycle, the dqm functions as the controller of output buffers. dqm is also used for device selection, byte selection and bus control in a memory system.
etrontech em63 b 165 ts rev . 2.0 18 jun . / 20 16 table 12. absolute maximum rating symbol item values unit note v in , v out input, output voltage - 1.0 ~ 4.6 v 1 v dd , v ddq power supply voltage - 1.0 ~ 4.6 v 1 t a ambient temperature - 4 0 ~ 85 c 1 t stg storage temperature - 5 5 ~ 150 c 1 t solder soldering temperature (10 second s ) 260 c 1 p d pow er dissipation 1 w 1 i o s short circuit output current 50 ma 1 table 13. recommended d.c. operating conditions (v dd = 3.3v ? a = - 4 0~ 85 c) symbol parameter min. typ. max. unit note v dd power supply voltage 3.0 3. 3 3.6 v 2 v ddq power supply volta ge(for i/o buffer) 3.0 3.3 3.6 v 2 v ih lvttl input high voltage 2.0 - v ddq +0.3 v 2 v il lvttl input low voltage - 0.3 - 0.8 v 2 i il input leakage current ( 0v ? vin ? vdd, all other pins not under test = 0v ) - 10 - 10 ? i o z output leakage current outp ut disable, 0v ? v out ? v ddq ) - 10 - 10 ? v oh lvttl output "h" level voltage ( i out = - 2ma ) 2.4 - - v v ol lvttl output "l" level voltage ( i out = 2ma ) - - 0.4 v table 14. capacitance (v dd = 3.3v, t a = 25 c) symbol parameter min. max. uni t c i input capacitance 3.5 5.5 pf c i/o input/output capacitance 4 6 pf note: these parameters are periodically sampled and are not 100% tested.
etrontech em63 b 165 ts rev . 2.0 19 jun . / 20 16 table 15. d.c. characteristics (v dd = 3.3v ? a = - 4 0~ 85 c) description/test condition symbol - 5 i - 6 i - 7 i unit note max. operating current t rc ? t rc (min), outputs open , one bank active i dd1 130 120 110 ma 3 precharge standby current in non - power down mode t ck = 15ns , cs# ? v ih (min), cke ? v ih input signals are changed every 2clks i dd2n 60 50 40 precharge standby current in non - power down mode t ck = ? , clk ? v il (max), cke ? v ih i dd2ns 36 36 36 precharge standby current in power down mode t ck = 15ns , cke ? v il (max) i dd2p 4 4 4 precharge standby current in power down mode t ck = ? , cke ? v il (ma x) i dd2ps 4 4 4 active standby current in non - power down mode t ck = 15ns , cke ? v ih (min), cs# ? v ih (min) input signals are changed every 2clks i dd3n 80 70 60 active standby current in non - power down mode cke ? v ih (min), clk ? v il (max), t ck = ? i dd3ns 80 70 60 operating current (burst mode) t ck =t ck (min), outputs open, multi - bank interleave i dd4 130 124 120 3, 4 refresh current t rc ? t rc (min) i dd5 170 160 150 3 self refresh current cke ? 0.2v ; for other inputs v ih R v dd - 0.2v, v il ? 0.2v i dd6 4 4 4
etrontech em63 b 165 ts rev . 2.0 20 jun . / 20 16 table 16. electrical characteristics and recommended a.c. operating conditions (v dd = 3.3v ? a = - 4 0~ 85 c) (note: 5, 6, 7, 8) symbol a.c. parameter - 5i - 6 i - 7 i unit note min. max. min. max. min. max. t rc row cycle time (same bank) 55 - 60 - 63 - ns t r f c refresh cycle time 55 - 60 - 63 - t rcd ras# to cas# delay (same bank) 15 - 18 - 21 - t rp precharge to refresh/row activate command (same bank) 15 - 18 - 21 - t rrd row activate to row activate delay (different banks) 10 - 1 2 - 14 - t mrd mode register set cycle time 10 - 12 - 14 - t ras row activate to precharge time (same bank) 40 120k 42 120 k 42 120 k t wr write recovery time 10 - 12 - 14 - t ck clock cycle time cl* = 2 - - 10 - 1 0 - 9 cl* = 3 5 - 6 - 7 - t ch clock high time 2 - 2 - 2.5 - 10 t cl clock low time 2 - 2 - 2. 5 - 10 t ac access time from clk (positive edge) cl* = 2 - - - 6 - 6 10 cl* = 3 - 4.5 - 5 - 5.4 t oh data output hold time 2 - 2.5 - 2.5 - 9 t lz data output low impedance 0 - 0 - 0 - t hz data output high impedance - 4.5 - 5 - 5.4 8 t is data/address/control input set - up time 1.5 - 1. 5 - 1. 5 - 10 t ih data/address/control input hold time 0.8 - 0.8 - 0.8 - 10 t pde power down exit set - up time t is+ t ck - t is+ t ck - t is+ t ck - t r efi average refresh interval time - 7.8 - 7.8 - 7.8 s t xsr exit self - refresh to any command t rc+ t is - t rc+ t is - t rc+ t is - ns * cl is cas latency. note: 1. stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. absolute maximum dc requirements conta in stress ratings only. functional operation at the absolute maximum limits is not implied or guaranteed. extended exposure to maximum ratings may affect device reliability. 2. all voltages are referenced to v ss . overshoot v ih (max) = 4.6v for pulse width 3 ns. undershoot v il (min) = - 1.0v for pulse width 3 ns. 3. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during every 2 t ck . 4. these parameters depend on the output loading. specified values are obtained with the output open. 5. power - up sequence is described in note 11. 6. a.c. test conditions
etrontech em63 b 165 ts rev . 2.0 21 jun . / 20 16 table 17. lvttl interface reference level of output signals 1.4v / 1.4v output load ref erence to the under output load (b) input signal levels 2.4v / 0.4v transition time (rise and fall) of input signals 1ns reference level of input signals 1.4v figure 1 8 .1 lvttl d.c. test load (a) figure 1 8 .2 lvttl a.c. test load (b) 7. transition times are measured between v ih and v il . transition ( rise and fall) of input signals are in a fixed slope (1 ns). 8. t hz defines the time in which the outputs achieve the open circuit c ondition and are not at reference levels. 9. if clock ris ing time is longer than 1 ns, ( t r / 2 - 0.5) ns should be added to the parameter. 10. assumed input rise and fall time t t ( t r & t f ) = 1 ns if t r or t f is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 11. power up sequence power up must be performed in the following sequence. 1) power must be applied to v dd and v ddq ( simultaneously) when cke = low , dqm = high and all input signals are held "nop" state. 2) start clock and maintain stable condition for minimum 200 ? s, then bring cke high and , it is recommended that dqm is held "high" (v dd levels) to ensure dq output is in high impedance. 3) all banks must be precharged. 4) mode register set command must be asserted to initialize the mode register. 5) a minimum of 2 auto - refresh dummy cycles must be required to stabilize the internal circuitry of the device. * the auto refresh command can be issue before or after mode register set command o u t p u t 1 . 2 k 3 0 p f 3 . 3 v 8 7 0 o u t p u t z 0 = 5 0 5 0 3 0 p f 1 . 4 v
etrontech em63 b 165 ts rev . 2.0 22 jun . / 20 16 timing waveforms figure 19 . ac parameters for write timing (burst length =4) t 0 t 1 t 2 d o n t c a r e t c h a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 t c l b e g i n a u t o p r e c h a r g e b a n k b r a x r b x r a y r a x c a x r b x c b x r a y c a y a x 0 a x 1 a x 2 a x 3 b x 0 b x 1 b x 2 b x 3 a y 0 a y 1 a y 2 a y 3 t r c d t r c t d a l t w r w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k a a c t i v a t e c o m m a n d b a n k b w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k b a c t i v a t e c o m m a n d b a n k a w r i t e c o m m a n d b a n k a p r e c h a r g e c o m m a n d b a n k a t i s t i s t i h t i h t i s b e g i n a u t o p r e c h a r g e b a n k a t i s t i h h i - z c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q
etrontech em63 b 165 ts rev . 2.0 23 jun . / 20 16 figure 2 0 . ac parameters for read timing (burst length=2, cas# latency=2) h i - z c l k c s # t 0 t 1 t 2 c k e d o n t c a r e r a s # t c h c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t c l b e g i n a u t o p r e c h a r g e b a n k b r a x r b x r a x c a x r b x c b x r a y r a y a x 0 a x 1 t r r d t r c r e a d c o m m a n d b a n k a a c t i v a t e c o m m a n d b a n k b r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k b a c t i v a t e c o m m a n d b a n k a t i s t i h t i h t i s t i s t i h t r a s t r c d t a c t l z t h z b x 0 b x 1 t h z t r p p r e c h a r g e c o m m a n d b a n k a t o h
etrontech em63 b 165 ts rev . 2.0 24 jun . / 20 16 figure 2 1 . auto refresh (burst length=4, cas# latency=2) t 0 t 1 t 2 d o n t c a r e p r e c h a r g e a l l c o m m a n d t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r a x c a x r a x a x 0 a x 1 t r p t r c a u t o r e f r e s h c o m m a n d a u t o r e f r e s h c o m m a n d a c t i v a t e c o m m a n d b a n k a r e a d c o m m a n d b a n k a t r c t r c d c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q
etrontech em63 b 165 ts rev . 2.0 25 jun . / 20 16 figure 2 2 . power on se quen c e and auto refresh h i - z t 0 t 1 t 2 d o n t c a r e i n p u t s m u s t b e s t a b l e f o r 2 0 0 s t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 t m r d m o d e r e g i s t e r s e t c o m m a n d h i g h l e v e l i s r e g u i r e d m i n i m u m f o r 2 r e f r e s h c y c l e s a r e r e q u i r e d t r p p r e c h a r g e a l l c o m m a n d 1 s t a u t o r e f r e s h ( * ) c o m m a n d 2 n d a u t o r e f r e s h ( * ) c o m m a n d a n y c o m m a n d n o t e ( * ) : t h e a u t o r e f r e s h c o m m a n d c a n b e i s s u e b e f o r e o r a f t e r m o d e r e g i s t e r s e t c o m m a n d c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 a 1 1 - a 1 2 d q m d q a d d r e s s k e y
etrontech em63 b 165 ts rev . 2.0 26 jun . / 20 16 figure 2 3 . self refresh entry & exit cycle note: to enter selfrefresh mode 1. cs#, ras# & cas# with cke should be low at the same clock cycle. 2. after 1 clock cycle, all th e inputs including the system clock can be don't care except for cke. 3. the device remains in selfrefresh mode as long as cke stays "low". 4. once the device enters selfrefresh mode, minimum t ras is required before exit from selfrefresh. to exit selfrefresh mod e 5. system clock restart and be stable before returning cke high. 6. enable cke and cke should be set high for valid setup time and hold time . 7. cs# starts from high. 8. minimum t xsr is required after cke going high to complete selfrefresh exit. 9. 8192 cycles of burst autorefresh is required before selfrefresh entry and after selfrefresh exit if the system uses burst refresh. t 0 t 1 t 2 d o n t c a r e s e l f r e f r e s h e n t r y t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 s e l f r e f r e s h e x i t a u t o r e f r e s h t i s h i - z t i s t i h * n o t e 1 * n o t e 2 * n o t e 3 , 4 t p d e * n o t e 5 * n o t e 6 * n o t e 7 t x s r * n o t e 8 h i - z * n o t e 9 c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q
etrontech em63 b 165 ts rev . 2.0 27 jun . / 20 16 figure 2 4 . 1 . clock suspension during burst read (using cke) (burst length=4, cas# latency=2) h i - z t 0 t 1 t 2 d o n t c a r e t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r a x r a x c a x a c t i v a t e c o m m a n d b a n k a r e a d c o m m a n d b a n k a a x 0 a x 1 a x 2 a x 3 t h z c l o c k s u s p e n d 1 c y c l e c l o c k s u s p e n d 2 c y c l e s c l o c k s u s p e n d 3 c y c l e s c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q
etrontech em63 b 165 ts rev . 2.0 28 jun . / 20 16 figure 2 4 . 2 . clock suspension during burst read (using cke) (burst length=4, cas# latency=3) h i - z t 0 t 1 t 2 d o n t c a r e t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r a x r a x c a x a c t i v a t e c o m m a n d b a n k a r e a d c o m m a n d b a n k a a x 0 a x 1 a x 2 a x 3 t h z c l o c k s u s p e n d 1 c y c l e c l o c k s u s p e n d 2 c y c l e s c l o c k s u s p e n d 3 c y c l e s c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q
etrontech em63 b 165 ts rev . 2.0 29 jun . / 20 16 figure 2 5 . clock suspension during burst write (using cke) (burst length=4) h i - z t 0 t 1 t 2 d o n t c a r e t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r a x r a x c a x a c t i v a t e c o m m a n d b a n k a w r i t e c o m m a n d b a n k a c l o c k s u s p e n d 1 c y c l e c l o c k s u s p e n d 2 c y c l e s c l o c k s u s p e n d 3 c y c l e s d a x 0 d a x 1 d a x 2 d a x 3 c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q
etrontech em63 b 165 ts rev . 2.0 30 jun . / 20 16 figure 2 6 . power down mode and clock suspension (burst leng th =4, cas# latency=2) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 t i s p o w e r d o w n m o d e e x i t t p d e p o w e r d o w n m o d e e n t r y r e a d c o m m a n d b a n k a c l o c k s u s p e n s i o n s t a r t p o w e r d o w n m o d e e x i t t i h r a x r a x c a x a x 0 a x 1 a x 3 a x 2 a c t i v e s t a n d b y c l o c k s u s p e n s i o n e n d p r e c h a r g e c o m m a n d b a n k a p o w e r d o w n m o d e e n t r y p r e c h a r g e s t a n d b y a n y c o m m a n d v a l i d t h z c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q
etrontech em63 b 165 ts rev . 2.0 31 jun . / 20 16 figure 2 7 . 1 . random column read (page within same bank) (burst length=4, cas# late ncy=2) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d c o m m a n d b a n k a r a w r a w c a x a w 0 a w 1 a y 2 p r e c h a r g e c o m m a n d b a n k a r a z c a w c a y r a z c a z a w 2 a w 3 a x 0 a x 1 a y 0 a y 1 a y 3 a z 0 r e a d c o m m a n d b a n k a r e a d c o m m a n d b a n k a a c t i v a t e c o m m a n d b a n k a r e a d c o m m a n d b a n k a c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q
etrontech em63 b 165 ts rev . 2.0 32 jun . / 20 16 figure 2 7 . 2 . random column read (page within same bank) (burst length=4, cas# latency=3) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d c o m m a n d b a n k a r a w r a w c a x a w 0 a w 1 a y 2 p r e c h a r g e c o m m a n d b a n k a r a z c a w c a y r a z c a z a w 2 a w 3 a x 0 a x 1 a y 0 a y 1 a y 3 r e a d c o m m a n d b a n k a r e a d c o m m a n d b a n k a a c t i v a t e c o m m a n d b a n k a r e a d c o m m a n d b a n k a c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q
etrontech em63 b 165 ts rev . 2.0 33 jun . / 20 16 figure 2 8 . random column write (page within same bank) (burst length=4) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k b t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 w r i t e c o m m a n d b a n k b r b w r b w c b x d b w 0 d b w 1 d b y 2 p r e c h a r g e c o m m a n d b a n k b c l k r b z c b w c b y r b z c b z d b w 2 d b w 3 d b x 0 d b x 1 d b y 0 d b y 1 d b y 3 w r i t e c o m m a n d b a n k b w r i t e c o m m a n d b a n k b a c t i v a t e c o m m a n d b a n k b w r i t e c o m m a n d b a n k b c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q d b z 0 d b z 1
etrontech em63 b 165 ts rev . 2.0 34 jun . / 20 16 figure 29 . 1 . random row read (interleaving banks) (burst length=8, cas# latency=2) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k b t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d c o m m a n d b a n k b r b x r b x r a x b x 0 b x 1 a x 0 p r e c h a r g e c o m m a n d b a n k b c l k r b y c b x c a x r b y c b y b x 2 b x 3 b x 4 b x 5 b x 6 b x 7 a x 1 a c t i v a t e c o m m a n d b a n k a r e a d c o m m a n d b a n k a a c t i v a t e c o m m a n d b a n k b r e a d c o m m a n d b a n k b c s # c k e w e # a 1 0 a x 6 a x 7 h i g h r a x a x 2 a x 3 a x 4 a x 5 t r c d t a c t r p a 0 - a 9 , a 1 1 - a 1 2 d q m d q b a 0 , 1 r a s # c a s #
etrontech em63 b 165 ts rev . 2.0 35 jun . / 20 16 figure 29 . 2 . random row read (interleaving banks) (burst le ngth=8, cas# latency=3) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k b t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d c o m m a n d b a n k b r b x r b x r a x b x 0 b x 1 a x 0 p r e c h a r g e c o m m a n d b a n k b r b y c b x c a x r b y c b y b x 2 b x 3 b x 4 b x 5 b x 6 b x 7 a x 1 a c t i v a t e c o m m a n d b a n k a r e a d c o m m a n d b a n k a a c t i v a t e c o m m a n d b a n k b r e a d c o m m a n d b a n k b a x 6 a x 7 h i g h r a x a x 2 a x 3 a x 4 a x 5 t r c d t a c t r p p r e c h a r g e c o m m a n d b a n k a b y 0 c l k c s # c k e w e # a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q b a 0 , 1 r a s # c a s #
etrontech em63 b 165 ts rev . 2.0 36 jun . / 20 16 figure 3 0 . random row write (interleaving banks) (burst length=8) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 w r i t e c o m m a n d b a n k a r a x r a x r b x d a x 3 d a x 4 d b x 3 p r e c h a r g e c o m m a n d b a n k a r a y c a x c b x r a y c a y d a x 5 d a x 6 d a x 7 d b x 0 d b x 1 d b x 2 d b x 4 a c t i v a t e c o m m a n d b a n k b w r i t e c o m m a n d b a n k b a c t i v a t e c o m m a n d b a n k a w r i t e c o m m a n d b a n k a d a y 1 d a y 2 h i g h r b x d b x 5 d b x 6 d b x 7 d a y 0 t r c d t r p p r e c h a r g e c o m m a n d b a n k b d a y 3 t w r * t w r * d a x 0 d a x 1 d a x 2 * t w r > t w r ( m i n . ) c l k c s # c k e w e # a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q b a 0 , 1 r a s # c a s #
etrontech em63 b 165 ts rev . 2.0 37 jun . / 20 16 figure 3 1 . 1 . read and write cycle (burst length=4, cas# latency=2) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d c o m m a n d b a n k a r a x r a x d a y 1 c a x c a z a x 0 a x 1 a x 2 a x 3 d a y 0 w r i t e c o m m a n d b a n k a t h e w r i t e d a t a i s m a s k e d w i t h a z e r o c l o c k l a t e n c y r e a d c o m m a n d b a n k a t h e r e a d d a t a i s m a s k e d w i t h a t w o c l o c k l a t e n c y a z 1 a z 3 c a y d a y 3 a z 0 c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q
etrontech em63 b 165 ts rev . 2.0 38 jun . / 20 16 figure 3 1 . 2 . read and write cycle (burst length=4, cas# latency=3) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d c o m m a n d b a n k a r a x r a x d a y 1 c l k c a x c a z a x 0 a x 1 a x 2 a x 3 d a y 0 w r i t e c o m m a n d b a n k a t h e w r i t e d a t a i s m a s k e d w i t h a z e r o c l o c k l a t e n c y r e a d c o m m a n d b a n k a t h e r e a d d a t a i s m a s k e d w i t h a t w o c l o c k l a t e n c y c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q a z 1 a z 3 c a y d a y 3 a z 0
etrontech em63 b 165 ts rev . 2.0 39 jun . / 20 16 figure 3 2 . 1 . interleaving column read cycle (burst length=4, cas# latency=2) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d c o m m a n d b a n k a r a x r a x r b x a x 0 a x 1 b y 0 r e a d c o m m a n d b a n k a r b x c a y c b w a x 2 a x 3 b w 0 b w 1 b x 0 b x 1 b y 1 a c t i v a t e c o m m a n d b a n k b r e a d c o m m a n d b a n k b r e a d c o m m a n d b a n k b p r e c h a r g e c o m m a n d b a n k b b z 2 b z 3 c b x c b y c a y c b z t r c d t a c r e a d c o m m a n d b a n k b r e a d c o m m a n d b a n k b b z 0 a y 0 a y 1 b z 1 p r e c h a r g e c o m m a n d b a n k a c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q
etrontech em63 b 165 ts rev . 2.0 40 jun . / 20 16 figure 3 2 . 2 . interleaved column read cycle (burst length=4, cas# latency=3) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d c o m m a n d b a n k a r a x r a x r b x a x 0 a x 1 b z 0 p r e c h a r g e c o m m a n d b a n k b r b x c a x c b x a x 2 a x 3 b x 0 b x 1 b y 0 b y 1 b z 1 a c t i v a t e c o m m a n d b a n k b r e a d c o m m a n d b a n k b p r e c h a r g e c o m m a n d b a n k a c b y c b z c a y t r c d t a c r e a d c o m m a n d b a n k b r e a d c o m m a n d b a n k a a y 2 a y 0 a y 1 a y 3 r e a d c o m m a n d b a n k b c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q
etrontech em63 b 165 ts rev . 2.0 41 jun . / 20 16 figure 3 3 . interleaved column write cycle (burst length=4) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 w r i t e c o m m a n d b a n k a r a x r a x r b w d a x 0 d a x 1 d b y 0 w r i t e c o m m a n d b a n k b c l k r b w c a x c b w d a x 2 d a x 3 d b w 0 d b w 1 d b x 0 d b x 1 d b y 1 a c t i v a t e c o m m a n d b a n k b w r i t e c o m m a n d b a n k b p r e c h a r g e c o m m a n d b a n k a c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q c b x c b y c a y t r c d w r i t e c o m m a n d b a n k b w r i t e c o m m a n d b a n k a d b z 0 d a y 0 d a y 1 d b z 1 w r i t e c o m m a n d b a n k b c b z t r r d > t r r d ( m i n ) t w r t w r d b z 2 d b z 3 p r e c h a r g e c o m m a n d b a n k b
etrontech em63 b 165 ts rev . 2.0 42 jun . / 20 16 figure 3 4 . 1 . auto precharge after read burst (burst length=4, cas# latency=2) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d c o m m a n d b a n k a r a x r a x c b x a x 0 a x 1 b x 0 r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k a r a z c a x c a y r b y c b y a x 2 a x 3 b x 1 a c t i v a t e c o m m a n d b a n k b r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k b a c t i v a t e c o m m a n d b a n k b a c t i v a t e c o m m a n d b a n k a a y 2 a y 3 h i g h r b x b x 2 b x 3 a y 0 a y 1 t r p r b y r b x r a z b y 2 b y 0 b y 1 r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k b b e g i n a u t o p r e c h a r g e b a n k b b e g i n a u t o p r e c h a r g e b a n k a c l k c s # c k e w e # a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q b a 0 , 1 r a s # c a s #
etrontech em63 b 165 ts rev . 2.0 43 jun . / 20 16 figure 3 4 . 2 . auto precharge after read burst (burst length=4, cas# latency=3) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d c o m m a n d b a n k a r a x r a x r b x b x 2 r b x c a x c b x a x 0 a x 1 a x 2 a x 3 b x 0 b x 1 b x 3 a c t i v a t e c o m m a n d b a n k b r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k a r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k b c a y a c t i v a t e c o m m a n d b a n k b a y 2 a y 0 a y 1 a y 3 r e a d w i t h a u t o p r e c h a r g e c o m m a n d b a n k b r b y t r p b e g i n a u t o p r e c h a r g e b a n k b b e g i n a u t o p r e c h a r g e b a n k a r b y c b y b y 2 b y 0 b y 1 h i g h c l k c s # c k e r a s # c a s # w e # b a 0 , 1 a 1 0 a 0 - a 9 , a 1 1 - a 1 2 d q m d q
etrontech em63 b 165 ts rev . 2.0 44 jun . / 20 16 figure 3 5 . auto precharge after write burst (burst length=4) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 w r i t e c o m m a n d b a n k a r a x r a x r b x d b x 2 r b x c a x c b x d a x 0 d a x 1 d a x 2 d a x 3 d b x 0 d b x 1 d b x 3 a c t i v a t e c o m m a n d b a n k b w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k a w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k b c a y a c t i v a t e c o m m a n d b a n k b d a y 2 d a y 0 d a y 1 d a y 3 w r i t e w i t h a u t o p r e c h a r g e c o m m a n d b a n k b r b y t d a l b e g i n a u t o p r e c h a r g e b a n k b b e g i n a u t o p r e c h a r g e b a n k a r b y c b y d b y 2 d b y 0 d b y 1 h i g h d b y 3 c l k c s # c k e w e # b a 0 , 1 a 1 0 d q m d q r a s # c a s # a 0 - a 9 , a 1 1 - a 1 2
etrontech em63 b 165 ts rev . 2.0 45 jun . / 20 16 figure 3 6 . 1 . full page read cycle (burst length=full page, cas# latency=2) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d c o m m a n d b a n k a r a x r a x a x + 1 r b x c a x r b x a x a x + 1 a x + 2 a x - 2 a x - 1 a x b x a c t i v a t e c o m m a n d b a n k b r e a d c o m m a n d b a n k b p r e c h a r g e c o m m a n d b a n k b c b x b u r s t s t o p c o m m a n d b x + 3 b x + 1 b x + 2 b x + 4 t h e b u r s t c o u n t e r w r a p s f r o m t h e h i g h e s t o r d e r p a g e a d d r e s s b a c k t o z e r o d u r i n g t h i s t i m e i n t e r v a l t r p r b y r b y b x + 5 b x + 6 h i g h f u l l p a g e b u r s t o p e r a t i o n d o e s n o t t e r m i n a t e w h e n t h e b u r s t l e n g t h i s s a t i s f i e d ; t h e b u r s t c o u n t e r i n c r e m e n t s a n d c o n t i n u e s b u r s t i n g b e g i n n i n g w i t h t h e s t a r t i n g a d d r e s s a c t i v a t e c o m m a n d b a n k b c l k c s # c k e w e # a 1 0 d q r a s # c a s # b a 0 , 1 a 0 - a 9 , a 1 1 - a 1 2 d q m
etrontech em63 b 165 ts rev . 2.0 46 jun . / 20 16 figure 3 6 . 2 . ful l page read cycle (burst length=full page, cas# latency=3) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d c o m m a n d b a n k a r a x r a x a x + 1 r b x c a x r b x a x a x + 1 a x + 2 a x - 2 a x - 1 a x b x a c t i v a t e c o m m a n d b a n k b r e a d c o m m a n d b a n k b p r e c h a r g e c o m m a n d b a n k b c b x b u r s t s t o p c o m m a n d b x + 3 b x + 1 b x + 2 b x + 4 t h e b u r s t c o u n t e r w r a p s f r o m t h e h i g h e s t o r d e r p a g e a d d r e s s b a c k t o z e r o d u r i n g t h i s t i m e i n t e r v a l t r p r b y r b y b x + 5 h i g h f u l l p a g e b u r s t o p e r a t i o n d o e s n o t t e r m i n a t e w h e n t h e b u r s t l e n g t h i s s a t i s f i e d ; t h e b u r s t c o u n t e r i n c r e m e n t s a n d c o n t i n u e s b u r s t i n g b e g i n n i n g w i t h t h e s t a r t i n g a d d r e s s a c t i v a t e c o m m a n d b a n k b c l k c s # c k e w e # a 1 0 d q r a s # c a s # b a 0 , 1 a 0 - a 9 , a 1 1 - a 1 2 d q m
etrontech em63 b 165 ts rev . 2.0 47 jun . / 20 16 figure 3 7 . full page write cycle (burst length=full page) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 w r i t e c o m m a n d b a n k a r a x r a x d a x + 1 r b x c a x r b x d a x d a x + 1 d a x + 2 d a x + 3 d a x - 1 d a x d b x a c t i v a t e c o m m a n d b a n k b w r i t e c o m m a n d b a n k b p r e c h a r g e c o m m a n d b a n k b c b x b u r s t s t o p c o m m a n d d b x + 3 d b x + 1 d b x + 2 d b x + 4 t h e b u r s t c o u n t e r w r a p s f r o m t h e h i g h e s t o r d e r p a g e a d d r e s s b a c k t o z e r o d u r i n g t h i s t i m e i n t e r v a l r b y r b y d b x + 5 h i g h f u l l p a g e b u r s t o p e r a t i o n d o e s n o t t e r m i n a t e w h e n t h e b u r s t l e n g t h i s s a t i s f i e d ; t h e b u r s t c o u n t e r i n c r e m e n t s a n d c o n t i n u e s b u r s t i n g b e g i n n i n g w i t h t h e s t a r t i n g a d d r e s s a c t i v a t e c o m m a n d b a n k b d a t a i s i g n o r e d c l k c s # c k e w e # a 1 0 d q r a s # c a s # b a 0 , 1 a 0 - a 9 , a 1 1 - a 1 2 d q m
etrontech em63 b 165 ts rev . 2.0 48 jun . / 20 16 figure 3 8 . byte read and write operation (bu rst length=4 , cas# latency= 2 ) t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d c o m m a n d b a n k a r a x r a x c a x u p p e r b y t e i s m a s k e d w r i t e c o m m a n d b a n k a l o w e r b y t e i s m a s k e d c a y r e a d c o m m a n d b a n k a l o w e r b y t e i s m a s k e d c a z c l k c s # c k e w e # a 1 0 d q 8 - d q 1 5 h i g h l o w e r b y t e i s m a s k e d r a s # c a s # b a 0 , 1 a 0 - a 9 , a 1 1 - a 1 2 l d q m u d q m a x 0 a x 1 a x 2 d a y 1 d a y 2 a z 1 a z 2 d q 0 - d q 7 a x 1 a x 2 a x 3 d a y 0 d a y 3 d a y 1 a z 0 a z 1 a z 2 a z 3 u p p e r b y t e i s m a s k e d
etrontech em63 b 165 ts rev . 2.0 49 jun . / 20 16 figure 39 . random row read (interleaving banks) (burst length= 4 , cas# latency= 2 ) t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k b t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r e a d b a n k b w i t h a u t o p r e c h a r g e r b u r b u r a u b v 0 r a u c b u c a u b u 0 b u 1 b u 2 b u 3 a u 0 a u 1 b v 1 a c t i v a t e c o m m a n d b a n k a a c t i v a t e c o m m a n d b a n k b r e a d b a n k a w i t h a u t o p r e c h a r g e r b v a c t i v a t e c o m m a n d b a n k a a v 0 b v 2 b v 3 a v 1 r e a d b a n k a w i t h a u t o p r e c h a r g e c b v t r p b e g i n a u t o p r e c h a r g e b a n k a b e g i n a u t o p r e c h a r g e b a n k b r a v c a v h i g h b e g i n a u t o p r e c h a r g e b a n k b b e g i n a u t o p r e c h a r g e b a n k a r b w r b v r a v r b w t r p t r p r e a d b a n k b w i t h a u t o p r e c h a r g e a u 2 a u 3 a v 2 a v 3 a c t i v a t e c o m m a n d b a n k b c l k c s # c k e w e # a 1 0 d q m d q r a s # c a s # b a 0 , 1 a 0 - a 9 , a 1 1 - a 1 2
etrontech em63 b 165 ts rev . 2.0 50 jun . / 20 16 figure 4 0 . full page random column read (burst length=full page, cas# latency=2) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 a c t i v a t e c o m m a n d b a n k b r a x c a x b y 1 r b x r b x c a y a x 0 a x 1 b x 0 a y 0 a y 1 b y 0 a z 0 r e a d c o m m a n d b a n k a r e a d c o m m a n d b a n k b p r e c h a r g e c o m m a n d b a n k b ( p r e c h a r g e t e m i n a t i o n ) c a z r e a d c o m m a n d b a n k a b z 0 a z 1 a z 2 b z 1 r e a d c o m m a n d b a n k a c b z t r p r b w r b w b z 2 r a x c b x c b y t r r d t r c d r e a d c o m m a n d b a n k b r e a d c o m m a n d b a n k b a c t i v a t e c o m m a n d b a n k b c l k c s # c k e r a s # c a s # w e # a 1 0 d q m d q b a 0 , 1 a 0 - a 9 , a 1 1 - a 1 2
etrontech em63 b 165 ts rev . 2.0 51 jun . / 20 16 figure 4 1 . full page random column write (burst length=full page) h i - z t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k a t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 a c t i v a t e c o m m a n d b a n k b r a x c a x d b y 1 r b x r b x c a y d a x 0 d a x 1 d b x 0 d a y 0 d a y 1 d b y 0 d a z 0 w r i t e c o m m a n d b a n k a w r i t e c o m m a n d b a n k b p r e c h a r g e c o m m a n d b a n k b ( p r e c h a r g e t e m i n a t i o n ) c a z w r i t e c o m m a n d b a n k a d b z 0 d a z 1 d a z 2 d b z 1 w r i t e c o m m a n d b a n k a c b z t r p r b w r b w d b z 2 r a x c b x c b y t r r d t r c d w r i t e c o m m a n d b a n k b w r i t e c o m m a n d b a n k b a c t i v a t e c o m m a n d b a n k b t w r w r i t e d a t a a r e m a s k e d c l k c s # c k e r a s # c a s # w e # a 1 0 d q m d q b a 0 , 1 a 0 - a 9 , a 1 1 - a 1 2
etrontech em63 b 165 ts rev . 2.0 52 jun . / 20 16 figure 4 2 . precharge termination of a burst (bur st length=4, 8 or full page, cas# latency=3) t 0 t 1 t 2 d o n t c a r e a c t i v a t e c o m m a n d b a n k b t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 r a x r a x a y 0 c a x d a x 0 d a x 1 a y 1 w r i t e c o m m a n d b a n k a a c t i v a t e c o m m a n d b a n k a a c t i v a t e c o m m a n d b a n k a r a y p r e c h a r g e c o m m a n d b a n k a a y 2 p r e c h a r g e c o m m a n d b a n k a c a y t w r r a z h i g h r a z r a y t r p r e a d c o m m a n d b a n k a p r e c h a r g e t e r m i n a t i o n o f a r e a d b u r s t t r p p r e c h a r g e t e r m i n a t i o n o f a w r i t e b u r s t w r i t e d a t a a r e m a s k e d c l k c s # c k e w e # a 1 0 d q m d q a 0 - a 9 , a 1 1 - a 1 2 r a s # c a s # b a 0 , 1
etrontech em63 b 165 ts rev . 2.0 53 jun . / 20 16 figure 4 3 . 54 pin tsop ii package outline drawing information symbol dimension in inch dimension in mm min nom max min nom max a --- --- 0.047 --- - -- 1.2 a1 0.002 --- 0.008 0.05 --- 0.2 a2 0.035 0.039 0.043 0.9 1.0 1.1 b 0.01 0.014 0.018 0.25 0.35 0.45 c 0.004 0.006 0.008 0.12 0.165 0.21 d 0.87 0.875 0.88 22.09 22.22 22.35 e 0.395 0.400 0.405 10.03 10.16 10.29 e --- 0.031 --- --- 0.8 --- he 0 .455 0.463 0.471 11.56 11.76 11.96 l 0.016 0.02 0.024 0.4 0.5 0.6 l1 0.032 --- --- 0.84 --- s --- 0.028 --- --- 0.71 --- y --- --- 0.004 --- --- 0.1 0 --- 8 0 --- 8

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